FBAR Filter Designer
FBAR Filter Designer Role Overview We are seeking an FBAR Filter Designer to lead the development of high
FBAR Filter Designer Role Overview We are seeking an FBAR Filter Designer to lead the development of high
of new interconnect technologies and IP for MCM, 2.5D, and 3D ICs, working alongside R&D, IP development, customers
with a focus on parallel interfaces. The job requires aspects of both a successful AE and R&D engineer. The candidate will work... alongside R&D, IP development, customers, and manufacturin…
, guide/mentor junior team members Think differently and out-of-the-box to stress the DUT and verify it in an efficient way... understanding of a complex protocol like PCI Express or other…
of new interconnect technologies and IP for MCM, 2.5D, and 3D ICs, working alongside R&D, IP development, customers
revenue targets. Executive Relationship Management: Cultivate and maintain C-suite and high-level executive relationships
-functional teams (Product, Engineering, Finance) with Nokia’s technology roadmap. Revenue Operations: Drive timely and accurate
(JMP, Python, R, or MATLAB) and database development for transitioning to high-volume manufacturing support. Professional
, and complex hardware/software debugging. Provide design-for-test (DFT) feedback to engineering teams. Mentor junior engineers
-delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial
, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Working closely with STA and DI Engineers design closure... with I/P DFT engineers & other stakeholders Debugging customer retu…
This individual will be a key member of the ASIC system-level verification team. Responsibilities include developing complex verification environments, creating comprehensive test plans, an…
signal integrity and power integrity, to apply to package designs Cadence APD (allegro package designer) experience
and design methodologies, and by organizing Q&A sessions with Broadcom technology experts See ahead, plan ahead, work ahead
As a Hardware Engineer, you will play a key role in designing and optimizing cutting-edge interface buffer chips for DDR/LP5/5X/6, chiplets and beyond in the latest FinFET process nodes. Yo…
and design methodologies, and by organizing Q&A sessions with Broadcom technology experts See ahead, plan ahead, work ahead
and design methodologies, and by organizing Q&A sessions with Broadcom technology experts See ahead, plan ahead, work ahead
, and architectural mentorship to mid-level and junior engineers on the team. Technical Execution Responsibilities RTL Design: Author
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