.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related discipline. With 10+ years
Job Title: Principal / Lead Engineer Location: San Jose, CA Job Summary: We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and…
Compliance testing Silicon characterization Performance tuning Analyze protocol traces and lab debug logs. Education: B....E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Comp…
in Transaction Layer development and enhancements. Support PCIe/CXL interoperability and advanced features. Drive integration... and coverage metrics. Support protocol compliance testing. D…
Job Title: Principal / Lead Engineer Location: San Jose, CA Job Summary: We are seeking a highly experienced... Principal/Lead Engineer to drive the architecture, development, integration,…
Job Title: Senior ATE Technician Location: San Jose, CA Job Description: General requirements for day-to-day support Docking and Undocking: Mechanically interfacing the ATE tester with Hand…
Job Title: Senior ATE Technician Location: San Jose, CA Job Description: General requirements for day-to-day
support Docking and Undocking: Mechanically interfacing the ATE tester with Handlers Loadboard/DIB Installation: Carefully... for the day. Load program and test parts as directed by the ATE…
Job Title: Senior ATE Technician Location: San Jose, CA Job Description: General requirements for day-to-day
for the day. Load program and test parts as directed by the ATE Engineer to collect data for performance reviews. Support
Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San Jose, CA Role Summary... expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protocol and DDR…
Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San Jose, CA Role Summary: We are looking for a Principal Design Engineer to lead RTL development and arc…
diagrams, and design documentation reflecting the new changes Participate in design reviews and mentor junior engineers
to support new CHI-G protocol requirements and DFI interface changes Own microarchitecture updates for command scheduling
Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San Jose, CA Role Summary...: We are looking for a Principal Design Engineer to lead RTL development and…
Job Title: Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Position Summary: We are seeking a highly experienced Verification Lead to own the end-t…
, LTSSM, PHY/SerDes interactions, UVM methodology, assertions, formal verification, emulation, and post-silicon debug support
Job Title: Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Position
Job Title: Verification Lead Memory Controller (CHI-G / DFI) Location: San Jose, CA Role Summary: We are seeking a Verification Lead to own the verification strategy, planning, and executio…
Job Title: Verification Lead Memory Controller (CHI-G / DFI) Location: San Jose, CA Role Summary: We are seeking... a Verification Lead to own the verification strategy, planning, and execu…
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