to support new CHI-G protocol requirements and DFI interface changes Own microarchitecture updates for command scheduling
diagrams, and design documentation reflecting the new changes Participate in design reviews and mentor junior engineers
Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San Jose, CA Role Summary...: We are looking for a Principal Design Engineer to lead RTL development and…
Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San Jose, CA Role Summary: We are looking for a Principal Design Engineer to lead RTL development and arc…
Job Title: Verification Lead Memory Controller (CHI-G / DFI) Location: San Jose, CA Role Summary: We are seeking... a Verification Lead to own the verification strategy, planning, and execu…
Tell us what is wrong with this job. After review it may be removed.
