Verification Lead – Memory Controller (CHI-G / DFI)
Job Title: Verification Lead Memory Controller (CHI-G / DFI) Location: San Jose, CA Role Summary: We are seeking... a Verification Lead to own the verification strategy, planning, and execu…
Job Title: Verification Lead Memory Controller (CHI-G / DFI) Location: San Jose, CA Role Summary: We are seeking... a Verification Lead to own the verification strategy, planning, and execu…
Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San Jose, CA Role Summary... expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protocol and DDR…
Job Title: Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Position Summary: We are seeking a highly experienced Verification Lead to own the end-t…
Job Title: Analog Layout Engineer Location: San Francisco, CA (Bay Area) Exp : Minimum 8 years and above Skill : 2nm, 3nm and 5nm process and high speed layout (MUST) Blocks : LDO ,ADC and…
Job Title: Physical Design Engineer Location: San Francisco, CA (Bay Area) Good understanding of Cadence tools (Innovous, Quantus, Voltus). (Must) Deep knowledge about industry standards in…
.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related discipline. With 10+ years
Job Title: QA Engineer Location: Chicago, IL or Iriving, TX (3 days onsite) 5+ years of experience in Quality Engineering, Software Testing, or Test Automation. Hands-on experience testing…
Job Title: Design Verification Lead Location: San Jose/Portland USA Position Summary: We are looking for a highly motivated Design Verification Lead with strong expertise in SystemVerilog/U…
Job Title: Senior ATE Technician Location: San Jose, CA Job Description: General requirements for day-to-day support Docking and Undocking: Mechanically interfacing the ATE tester with Hand…
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